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HUF76009P3, HUF76009D3S
Data Sheet December 2001
20A, 20V, 0.027 Ohm, N-Channel, Logic Level Power MOSFETs
THE HUF76009 is an application-specific MOSFET optimized for switching when used as the upper switch in synchronous buck applications. The low gate charge and low input capacitance results in lower driver and lower switching losses thereby increasing the overall system efficiency.
Features
* 20A, 20V - rDS(ON) = 0.027, VGS = 10V - rDS(ON) = 0.039, VGS = 5V * PWM optimized for synchronous buck applications * Fast Switching
Symbol
D
G
* Low Gate Charge - Qg Total 11nC (Typ)
S
Packaging
HUF76009D3S JEDEC TO-252AA
DRAIN (FLANGE) GATE SOURCE DRAIN (FLANGE)
HUFD76009P3 JEDEC TO-220AB
SOURCE DRAIN GATE
* Low Capacitance - CISS 470pF (Typ) - CRSS 50pF (Typ)
Ordering Information
PART NUMBER HUF76009P3 HUF76009D3S PACKAGE TO-220AB TO-252AA BRAND 76009P 76009D
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the HUF76009D3S in tape and reel, e.g., HUF76009D3ST.
Absolute Maximum Ratings
SYMBOL VDSS VDGR VGS ID ID IDM PD TJ, TSTG TL Tpkg RJC RJA NOTE: 1. TJ = 25oC to 125oC.
TC = 25oC, Unless Otherwise Specified PARAMETER HUF76009P3, HUF76009D3S 20 20 16 20 16 Figure 4 41 0.33 -55 to 150 300 260 3.04 62 100 UNITS V V V A A A W W/oC
oC oC oC oC/W oC/W oC/W
Drain to Source Voltage (Note 1) Drain to Gate Voltage (RGS = 20k) (Note 1) Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) Continuous (TC = 100oC, VGS = 5V) Pulsed Drain Current Power Dissipation Derate Above 25oC Operating and Storage Temperature Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s Package Body for 10s, See Techbrief TB334 Thermal Resistance Junction to Case, TO-220, TO-252 Thermal Resistance Junction to Ambient TO-220 Thermal Resistance Junction to Ambient TO-252
THERMAL SPECIFICATIONS
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
(c)2001 Fairchild Semiconductor Corporation HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 11) VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A (Figure 10) ID = 20A, VGS = 10V (Figures 8, 9) ID = 16A, VGS = 5V (Figure 8) SWITCHING SPECIFICATIONS (VGS = 5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 10V, ID = 16A VGS = 5V, RGS = 27, (Figures 14, 18, 19) 9 115 19 34 186 80 ns ns ns ns ns ns 1 0.022 0.032 3 0.027 0.039 V IGSS VGS = 16V 20 1 250 100 V A A nA TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 20V, VGS = 0V, f = 1MHz (Figure 12) 470 350 50 pF pF pF Qg(TOT) Qg(TOT) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 10V, ID = 16A, Ig(REF) = 1.0mA, (Figures 13, 16, 17) 10.7 5.7 0.5 1.7 2.2 13 6.9 0.6 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 10V, ID = 20A VGS = 10V, RGS = 27 (Figures 15, 18, 19) 5.3 95 37 33 150 105 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 20A ISD = 10A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 16A, dISD/dt = 100A/s ISD = 16A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.0 33 30 UNITS V V ns nC
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 20 VGS = 10V 15 VGS = 5V 10 0.8 0.6 0.4 0.2 0 25
5
0
25
50
75
100
125
150
0 25
50
75
100
125
150
TA , AMBIENT TEMPERATURE (oC)
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
100
VGS = 10V
I = I25
150 - TC 125
VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S Typical Performance Curves
200 100 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 30 100s
(Continued)
40 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
20
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 50 1ms
10 TJ = 25oC 0 2
10ms
TJ = 150oC TJ = -55oC 3 4 5
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
40 VGS = 10V ID , DRAIN CURRENT (A) 30 VGS = 5V VGS = 4.5V TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 20 VGS = 4V 10 VGS = 3.5V VGS = 3V 0 0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V) rDS(ON) , DRAIN TO SOURCE ON RESISTANCE (m)
60 ID = 16A 50 ID = 5A 40 ID = 10A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
30
20
10 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE 1.4
1.2 VGS = VDS, ID = 250A
1.0
1.2
1.0
0.8
0.8 VGS = 10V, ID = 20A 0.6 -80 -40 0 40 80 120 160
0.6 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1000 1.1 C, CAPACITANCE (pF) CISS = CGS + CGD
(Continued)
2000
COSS CDS + CGD
1.0
CRSS = CGD
100 VGS = 0V, f = 1MHz -40 0 40 80 120 160 50 0.1 1 VDS , DRAIN TO SOURCE VOLTAGE (V) 10 20 TJ , JUNCTION TEMPERATURE (oC)
0.9 -80
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 10V 8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
150 VGS = 5V, VDD = 10V, ID = 16A 125 SWITCHING TIME (ns) tr 100 75 50 25 12 td(ON) 0 0 10 20 30 40 50 RGS , GATE TO SOURCE RESISTANCE () tf td(OFF)
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 16A ID = 10A ID = 5A 0 3 6 Qg, GATE CHARGE (nC) 9
2
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
100 tr SWITCHING TIME (ns) 80 VGS = 10V, VDD = 10V, ID = 20A 60 td(OFF)
40 tf 20 td(ON) 0 0 10 20 30 40 50 RGS , GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S Test Circuits and Waveforms
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(TOT) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S PSPICE Electrical Model
.SUBCKT HUF76009P3 2 1 3 ;
CA 12 8 5.6e-10 CB 15 14 5.0e-10 CIN 6 8 4.5e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev 16 March 2000
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 4.6e-9 LSOURCE 3 7 4.7e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.0e-3 RGATE 9 20 4.0 RLDRAIN 2 5 10 RLGATE 1 9 46 RLSOURCE 3 7 47 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.4e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),3))} .MODEL DBODYMOD D (IS = 3.4e-13 RS = 1.0e-2 TRS1 = 2e-3 TRS2 = 8e-7 CJO = 1.05e-9 TT = 1.18e-8 XTI = 5 M = 0.42) .MODEL DBREAKMOD D (RS = 1.3e- 1TRS1 = 0TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 3.2e-1 0IS = 1e-3 0N = 10 M = 0.6) .MODEL MMEDMOD NMOS (VTO = 2.38 KP = 12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RS = 0.03 RG = 4) .MODEL MSTROMOD NMOS (VTO = 2.87 KP = 28 LAMBDA = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.95 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.7e- 4TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 9.8e-3 TC2 = 2.85e-5) .MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 5.05e-6) .MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.48e-3 TC2 = -5e-6) .MODEL RVTEMPMOD RES (TC1 = -1.68e- 3TC2 = 8e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.7 VOFF= -2.0) VON = -2.0 VOFF= -4.7) VON = -1.0 VOFF= 0.3) VON = 0.3 VOFF= -1.0)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
-
EBREAK 11 7 17 18 25.9 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S SABER Electrical Model
REV 16 March 2000 template HUF76009P3 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 3.4e-13, rs = 1.0e-2, trs1 = 2e-3, trs2 = 8e-7, cjo = 1.05e-9, tt = 1.18e-8, xti = 5, m = 0.42) dp..model dbreakmod = (rs = 1.3e-1, trs1 = 0, trs2 = 0) dp..model dplcapmod = (cjo = 3.2e-10, isl = 10e-30, nl = 10, m = 0.6) m..model mmedmod = (type=_n, vto = 2.38, kp = 12, is = 1e-30, tox = 1, rs = 0.03) m..model mstrongmod = (type=_n, vto = 2.87, kp = 28, lambda = 0.02, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.95, kp = 0.08, is = 1e-30, tox = 1, rs = 0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.7, voff = -2.0) DPLCAP 5 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -4.7) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.3) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -1.0) RSLC1 c.ca n12 n8 = 5.6e-10 c.cb n15 n14 = 5.0e-10 c.cin n6 n8 = 4.5e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 4.6e-9 l.lsource n3 n7 = 4.7e-9
GATE 1 RLGATE CIN LGATE 51 RSLC2 ISCL
LDRAIN DRAIN 2 RLDRAIN
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18
MSTRO 8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 0 res.rdrain n50 n16 = 1.0e-3, tc1 = 9.8e-3, tc2 = 2.85e-5 res.rgate n9 n20 = 4.0 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 46 res.rlsource n3 n7 = 47 res.rslc1 n5 n51= 1e-6, tc1 = 5e-3, tc2 = 5.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.4e-2, tc1 = 1.5e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.68e-3, tc2 = 8e-7 res.rvthres n22 n8 = 1, tc1 = -1.48e-3, tc2 = -5e-6 spe.ebreak n11 n7 n17 n18 = 25.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 3)) } }
S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 15
-
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP 19 IT
VBAT +
-
-
8 RVTHRES
22
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S SPICE Thermal Model
REV 16 March 2000 T76009 CTHERM1 th 6 9.5e-4 CTHERM2 6 5 2.4e-3 CTHERM3 5 4 3.9e-3 CTHERM4 4 3 4.3e-3 CTHERM5 3 2 5.9e-3 CTHERM6 2 tl 3.0e-2 RTHERM1 th 6 2.0e-2 RTHERM2 6 5 1.1e-1 RTHERM3 5 4 2.75e-1 RTHERM4 4 3 5.3e-1 RTHERM5 3 2 7.1e-1 RTHERM6 2 tl 7.8e-1
th JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model T76009 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 9.5e-4 ctherm.ctherm2 6 5 = 2.4e-3 ctherm.ctherm3 5 4 = 3.9e-3 ctherm.ctherm4 4 3 = 4.3e-3 ctherm.ctherm5 3 2 = 5.9e-3 ctherm.ctherm6 2 tl = 3.0e-2 rtherm.rtherm1 th 6 = 2.0e-2 rtherm.rtherm2 6 5 = 1.1e-1 rtherm.rtherm3 5 4 = 2.75e-1 rtherm.rtherm4 4 3 = 5.3e-1 rtherm.rtherm5 3 2 = 7.1e-1 rtherm.rtherm6 2 tl = 7.8e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
E H1 A A1 SEATING PLANE D L2 1 3 L
INCHES SYMBOL A A1 b b1 b2 b3 c D E e e1 H1 J1 L L1 MIN 0.086 0.018 0.028 0.033 0.205 0.190 0.018 0.270 0.250 MAX 0.094 0.022 0.032 0.045 0.215 0.022 0.295 0.265
MILLIMETERS MIN 2.19 0.46 0.72 0.84 5.21 4.83 0.46 6.86 6.35 MAX 2.38 0.55 0.81 1.14 5.46 0.55 7.49 6.73 NOTES 4, 5 4, 5 4 4, 5 2 4, 5 7 7 4, 6 3 2
b2
b e e1
TERM. 4
b1
L1
c
J1 0.265 (6.7)
0.090 TYP 0.180 BSC 0.035 0.040 0.100 0.020 0.025 0.170 0.045 0.045 0.115 0.040 -
2.28 TYP 4.57 BSC 0.89 1.02 2.54 0.51 0.64 4.32 1.14 1.14 2.92 1.01 -
L3
b3
0.265 (6.7)
L2 L3
0.070 (1.8) 0.118 (3.0) BACK VIEW 0.063 (1.6) TYP 0.090 (2.3) TYP MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS
NOTES: 1. These dimensions are within allowable dimensions of Rev. B of JEDEC TO-252AA outline dated 9-88. 2. L3 and b3 dimensions establish a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 11 dated 1-00.
1.5mm DIA. HOLE
4.0mm USER DIRECTION OF FEED 2.0mm 1.75mm C L
TO-252AA
16mm TAPE AND REEL
16mm
8.0mm
COVER TAPE
22.4mm
13mm 330mm 50mm
GENERAL INFORMATION 1. 2500 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
16.4mm
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
HUF76009P3, HUF76009D3S TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A OP Q H1 D E1 45o D1 TERM. 4 E A1
INCHES SYMBOL A A1 b b1 c D D1 E E1 e e1 MIN 0.170 0.048 0.030 0.045 0.014 0.590 0.395 MAX 0.180 0.052 0.034 0.055 0.019 0.610 0.160 0.410 0.030 0.100 TYP 0.200 BSC 0.235 0.100 0.530 0.130 0.149 0.102 0.255 0.110 0.550 0.150 0.153 0.112
MILLIMETERS MIN 4.32 1.22 0.77 1.15 0.36 14.99 10.04 MAX 4.57 1.32 0.86 1.39 0.48 15.49 4.06 10.41 0.76 2.54 TYP 5.08 BSC 5.97 2.54 13.47 3.31 3.79 2.60 6.47 2.79 13.97 3.81 3.88 2.84 NOTES 3, 4 2, 3 2, 3, 4 5 5 6 2 -
L1
b1 b c
L 60o 1 2 3
e e1
J1
H1 J1 L L1 OP Q NOTES:
1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimensio n :Inch. 8. Revision 2 dated 7-97.
(c)2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B
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OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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